Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
As advanced metal-oxide-semiconductor (MOS) technology continues to scale and move into the deep-sub-micron geometry dimensions, the optimization of source/drain regions has become complex. Conventional techniques that are employed to form the source region and the drain region often result in poor topology in a surface of the semiconductor substrate and, in particular, in surfaces of the source region and the drain region. Poor topology of the semiconductor substrate affects formation of subsequent features that overlie the semiconductor substrate and can lead to void formation, which may ultimately result in device failure. Cycles of medium to high dose ion implantation are often used to form the source region and the drain region, as well as various extension regions for the source region and the drain region. Each cycle of ion implantation is generally accompanied by patterning of a mask to limit ion implantation to desired regions of the semiconductor substrate, followed by stripping the mask and cleaning the semiconductor substrate after each ion implantation. However, it is believed that stripping the mask and cleaning the semiconductor substrate adversely impacts the surface topology of the semiconductor substrate by removing material therefrom. The adverse impact on the surface topology of the semiconductor substrate is compounded by numerous ion implantations. In this regard, the adverse impact on surface topology is particularly pronounced for multi-voltage threshold devices, which have been developed to include transistors and other devices on the semiconductor substrate that have different threshold voltages. The multi-voltage threshold devices are useful to increase performance without an increase in power requirements and are generally formed using varying degrees of ion implantation to form the source region and the drain region. Low, moderate or regular, and highly doped source regions and drain regions are formed depending upon whether a particular transistor is to have a high voltage threshold, a moderate voltage threshold, or a low voltage threshold within the multi-voltage threshold device. Formation of the low, moderate or regular, and highly doped source regions and drain regions, as well as formation of extension regions for the source region and the drain region, generally require separate masking, ion implantation, mask stripping, and substrate cleaning, thereby impacting topology of the semiconductor substrate as described above.
Accordingly, it is desirable to provide methods of forming semiconductor devices with minimized damage to semiconductor substrate surfaces resulting from mask stripping and substrate cleaning after ion implantation. It is also desirable to provide such methods that minimize damage to the semiconductor substrate surfaces even when numerous cycles of masking, ion implantation, mask stripping and substrate cleaning are employed. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.